FIG. 1 is a block diagram of a conventional semiconductor memory device 10, such as a dynamic random access memory (DRAM) device that includes a control circuit 20, address buffer 30, row decoders 40, memory cell array 50, sense amplifiers 60, data output circuit 70, and column decoders 80, which are configured as shown. The control circuit 20 is used to control operations of the address buffer 30 and the row decoders 40 responsive to one or more control signals. The address buffer 30 receives an address A0-An AND logic circuit divides the address into a row address and a column address, which are respectively used to drive the row decoders 40 and column decoders 80. The output of the row decoders 40 is used to select particular word lines of the memory cell array 50. The output of the column decoders 80 is used to select particular bits of words stored in the memory cell array 50 via the sense amplifiers 60 and the data control circuit 70. The data output circuit 70 may. for example, output data DQ0-DQ7 corresponding to eight bits from a selected word.
Data may be output through the data output circuit 70 through a burst read operation. The burst length of a burst read operation corresponds to the number bits. bytes, and/or words that are output in one burst read operation. The column address strobe (CAS) latency is the number of clock cycles from the beginning of a rising edge of a clock until the first data are output. FIG. 2 illustrates the data output circuit 70 in more detail. The data output circuit 70 includes an ordering circuit 200 a multiplexer circuit 210, and a pulse generator 220 that are configured as shown. The ordering circuit 200 is coupled to the memory core 230 and receives data (D0, D1, D2, D3) therefrom for output responsive to a read command. The ordering circuit 200 may be implemented as a switching circuit that outputs data onto particular output lines of the ordering circuit based on the column address associated with the read command. In the example shown in FIG. 2, if the column address is 01 and the memory device is operating in sequential mode, then the output order for the data is D1, D2, D3, and D0. Accordingly, the ordering circuit 200 switches data D1 onto the data output line DO0, switches data D2 onto the data output line DO1, switches data D3 onto the data output line DO2, and switches data D0 onto the data output line DO3. The switches CDQ_1, CDQ_2, CDQ_3 and CDQ_4 are closed and opened in order responsive to the CDQ signal output by the pulse generator 220 to output the data D1, D2, D3, and D0 in order onto the output line DOP. Table 1 below illustrates the data output order for burst lengths of 4 and 8 based on starting column address for both a sequential mode of operation and an interleave mode of operation.
TABLE 1Burst LengthCASequentialInterleave40000, 1, 2, 30, 1, 2, 340011, 2, 3, 01, 0, 3, 240102, 3, 0, 12, 3, 0, 140113, 0, 1, 23, 2, 1, 080000, 1, 2, 3, 4, 5, 6, 70, 1, 2, 3, 4, 5, 6, 780011, 2, 3, 4, 5, 6, 7, 01, 0, 3, 2, 5, 4, 7, 680102, 3, 4, 5, 6, 7, 0, 12, 3, 0, 1, 6, 7, 4, 580113, 4, 5, 6, 7, 0, 1, 23, 2, 1, 0, 7, 6, 5, 481004, 5, 6, 7, 0, 1, 2, 34, 5, 6, 7, 0, 1, 2, 381015, 6, 7, 0, 1, 2, 3, 45, 4, 7, 6, 1, 0, 3, 281106, 7, 0, 1, 2, 3, 4, 56, 7, 4, 5, 2, 3, 0, 181117, 0, 1, 2, 3, 4, 5, 67, 6, 5, 4, 3, 2, 1, 0
Unfortunately, the ordering circuit 200 consumes chip area in an integrated circuit memory device and physically switching data read from the memory core onto output lines of the ordering circuit can introduce delay in outputting data.